The final PCM data is output from this chip to the D/A converters.

· AES/ EBU chip MB653806 (IC34)

This is the interface for digital audio (AES/EBU format). and is also a phase comparator for the PLL c~



This consists of low pass filters (FL9-FL12) for sampling' a serial A/D convertor (IC21), an XLR input amp

IC8), fow pass filters for playback (FL1-FL8), a parallel D/A convertor (IC26), a sampling monitor circuit (IC23) and a muting circuit QC9- IC11).


I About the PLL (Phase Locked Loop) circuit i order to receive a digital audio signal which contains jitter frequency instability) and to make the master samplinq equency variable, the S-770 has two PLL circuits; PLI 1 A nd PLL2.(Fig.a)




PLLl operation

In this PLL circuit, control signals FO and Fl are input to VC01 (D300, tC33) to switch the master sampling frequency between 44.1k and 48k.

When recording digital audio, the analog switch (4066, IC32) is switched so that the control voltage from LPF1 operates VC01, in order to make the PLL circuit operate. When not recording digital audio, the analog switch is switched to fix the control voltage.

When input is switched from analog to digital, or when the digital input is unstable, the UNLOCK signal from the AES/EBU chip (MB653806, IC34) causes the LFQ (IC31) to operate, and when the PLL becomes stable, to cease operating.



PLL2 operation

PLL2 is the circuit which ultimately determines master clock that controls the sampler chip (IC38). Thus, if this circuit does not operate correctly, the pitch will be unstable. The phase comparator of the AES/E9lJ chip (tC34) outputs a control signal according to the sampling frequency and jitter, and the changing pulse